1. Field of the Invention
The present invention relates to a power amplifier which amplifies input power by means of an amplifying transistor and outputs it. The invention also relates to an MMIC using this power amplifier.
2. Background Art
Japanese Laid-Open Patent Publication No. 2008-245081 discloses a power amplifier in which a gate voltage suppression resistance is connected between the gate terminal of the amplifying transistor and the gate voltage terminal for supplying a gate voltage to the gate terminal.
The gate of the amplifying transistor of a power amplifier receives alternately high power and low power. When the power applied to the gate transitions from a high level to a low level, the drain current of the amplifying transistor also decreases. It should be noted that within a certain period of time after the transition of the power level, the drain current may drop by an amount greater than necessary. (This phenomenon is referred to herein as “rapid reduction of the drain current.”) In some cases, this drop in the drain current has resulted in decreased gain of the power amplifier and increased noise factor.